The various embodiments described herein relate to the field of multiprocessor systems, and more specifically to the field of aligning timing signals among processors to achieve time synchronous operation.
In a typical multiprocessor architecture (e.g., architecture of state-of-the art servers), correct time of day (TOD) information for each processor is of utmost importance. The TOD information is used for database time stamp operations and generally for transaction processing. In such a multiprocessor environment, the TOD information may be synchronized between all processors using physical and usually redundant interconnections that propagate a TOD stepping signal in a serial manner.
U.S. Publication No. 2006/0179364 A1 discloses a stepping pulse network, which comprises an alignment element that allows selecting a stepping signal from among two oscillator signals. As a result, two TOD oscillators provide at least one valid oscillator signal even in the event of a failure. A designated master chip observes a signal criterion of the valid oscillator signal and uses the valid oscillator signal to generate an immediate TOD stepping signal.
FIG. 1 shows a schematic of an alignment element 01 with two oscillator signals 04 and 05 as input and a control signal 06, which is used to select an active path 02, 03 as a master path and the oscillator signal 04, 05 as a master signal to generate an output stepping signal 07, 08 at an output of the alignment element 01. The output stepping signal 07, 08 is used to generate a TOD stepping signal within a stepping pulse network connected with the output of the alignment element 01.
In the known solution provided by the state of the art, output stepping signals 07, 08 are generated by counters with an adjustable threshold value (FIG. 2). The threshold value 10 for the master path M, which in FIG. 2 is path 03, remains constant and is used to generate the output stepping signal 08 of the master path 03 as a function of the connected oscillator signal 05. The threshold value 09 of the slave path S, which in FIG. 2 is path 02, is computed such that the generated output stepping signal 07 of the slave path S is exactly aligned to the output stepping signal 08 of the master path M. In the event of a path switch 11, the threshold value 12 of the former slave path S 02, which becomes the new master path M, is frozen to the threshold value of the new master path M. The threshold value 13 of the new slave path S 03 is adjusted as exemplarily shown in FIG. 2.
This state-of-the-art routine works correctly as long as the offset between two oscillator signals 04, 05 only differs by one cycle within a step and none of the oscillator signals 04, 05 fails while being the input signal for the master path M.
When the oscillator signals differ by more than one cycle per step, the relevant logic needs some time to achieve the alignment. During this timeframe, no path switch can be done without inducing a phase jump in the output stepping signal. Thus, the switch may be delayed until the control loop has reached its target value and the output stepping signals are aligned correctly again. A drawback of this solution is that in some scenarios it can take a long time until the switch is completed. Furthermore, there is no way to handle sudden failures of the oscillator signal master path. The logic can only be used to manually switch the output stepping signal to one path while the oscillator of the other path is being replaced.